1. Technical Field
The present disclosure relates to a semiconductor device and to a method of manufacturing a semiconductor device. More particularly, the present disclosure relates to a semiconductor device including a transistor having a vertical channel region and a transistor having a horizontal channel region, and to a method of manufacturing the semiconductor device including transistors having channel regions generated different directions.
2. Description of the Related Art
In a conventional semiconductor memory device, a transistor may include a source region, a drain region and a gate electrode. Charges such as electrons or holes may generate from the source region and may flow into the drain region. The gate electrode may control the flow of the charges between the source region and the drain region. A channel region may be generated at a portion of a semiconductor substrate located between the source and the drain regions. To electrically insulate the channel region from the gate electrode, a gate insulation layer may be disposed between the gate electrode and the substrate.
As for the conventional transistor, a gate structure typically includes a gate insulation layer and a gate electrode sequentially stacked on a substrate. Source/drain regions of the transistors are located at portions of the substrate adjacent to the gate structure. Thus, a channel region of the transistor is horizontally formed at a portion of the substrate between the source/drain regions.
As a current semiconductor memory device has a high integration degree, a gate electrode of a transistor in the semiconductor device may have a considerably reduced length, so that a short channel effect may occur in the transistor having the gate electrode of a minute length. When the short channel effect generates in the transistor, the transistor may encounter various difficulties, such as for example, an increase of a leakage current, a decrease of a thresh hole voltage, a continuous increase of a drain induced current, etc. Meanwhile, the transistor has been used to provide a design rule below a critical dimension of a photolithography process as the semiconductor memory device has been an integration degree above giga bites. Hence, the conventional transistor having a vertical channel region between source/drain regions may not be properly employed in the highly integrated semiconductor memory device.
To improve the integration degree of the semiconductor memory device, there is provided a transistor having a structure wherein a source region and a drain region arranged along a vertical direction relative to a substrate. Such a transistor has a channel region vertically formed between the source and the drain regions. In the transistor having the vertical channel region, an active region of the transistor may be protruded from the substrate. The source region and the drain region may be formed at an upper portion and a lower portion of the active region.
The channel region of the transistor may be generated at a portion of the active region along a direction perpendicular with respect to the substrate. A word line of the transistor may enclose the active region in a horizontal direction relative to the substrate, and a bit line of the transistor may be disposed below the word line. The bit line may be formed by doping impurities into portions of the active region, such that the bit line may have a resistance substantially larger than that of a bit line in the convention transistor. However, when the bit line has an increased resistance, a signal may not be sufficiently applied to the transistor, thereby possibly deteriorating electrical characteristics of the semiconductor device having the transistor.
In the meantime, a semiconductor memory device generally includes a memory cell area and a logic area. A vertical channel transistor may be disposed in the memory cell area whereas a planar channel transistor may be provided in the logic area. The planar transistor in the logic area may be a P type metal oxide semiconductor (PMOS) transistor or an N type MOS (NMOS) transistor. As the semiconductor memory device may need a very high integration degree, the planar channel transistor should have a high integration degree. However, a p-n junction between adjacent planar channel transistors and/or the planar transistor and the vertical channel transistor may be frequently caused by migration of impurities, so that the electrical characteristics semiconductor memory device may be deteriorated.
Thus, there is still a need in the art for a semiconductor device which includes a bit line which has significantly reduced resistance in a cell area of the semiconductor device in comparison with that of the conventional semiconductor device and also wherein a p-n junction between the cell area and the logic area of the semiconductor device is prevented.